The present invention relates to the field of programmable logic integrated circuits. More specifically, the present invention provides an enhanced programmable logic architecture, improving upon the composition, configuration, and arrangements of logic array blocks and logic elements and also the interconnections between these logic array blocks and logic elements.
Programmable Logic Devices (PLDs) are well known to those in the electronic art. Such programmable logic devices are commonly referred as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), PLDs (Programmable Logic Devices), EPLDs (Erasable Programmable Logic Devices), EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for a specific application. Such devices include, for example, the well-known, Classic(trademark), and MAX(copyright) 5000, MAX(copyright) 7000, and FLEX(copyright) 8000 EPLDs made by Altera Corp.
PLDs are generally known in which many logic array blocks (LABs) are provided in a two-dimensional array. Further, PLDs have an array of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the logic array blocks. These conductors may be organized into an interconnect bus, which may be referred to as a programmable interconnect array (PIA), global horizontal interconnect (GHs), or global vertical interconnects (GVs). LABs contain a number of programmable logic elements (LEs) or macrocells which provide relatively elementary logic functions such as NAND, NOR, and exclusive OR. LEs also provide sequential or registered logic functions.
Resulting from the continued scaling and shrinking of semiconductor device geometries, which are used to form integrated circuits (also known as xe2x80x9cchipsxe2x80x9d), integrated circuits have progressively become smaller and denser. For programmable logic, it becomes possible to put greater numbers of programmable logic elements onto one integrated circuit. Furthermore, as the number of elements increases, it becomes increasingly important to improve the techniques and architectures used for interconnecting the elements and routing signals between the logic blocks. In particular, it is important to provide enough interconnection resources between the programmable logic elements so that the capabilities of the logical elements can be fully utilized and so that complex logic functions (e.g., requiring the combination of multiple LABs and LEs) can be performed, without providing so much interconnection resources that there is a wasteful excess of this type of resource.
While such devices have met with substantial success, such devices also meet with certain limitations, especially in situations in which the provision of additional or alternative types of interconnections between the logic modules would have benefits sufficient to justify the additional circuitry and programming complexity. Such additional interconnection paths may be desirable for making frequently needed kinds of interconnections, for speeding certain kinds of interconnections, for allowing short distance connections to be made without tying up a more general-purpose interconnection resource such as long-distance interconnect. There is also a continuing demand for logic devices with larger capacity. This produces a need to implement logic functions more efficiently and to make better use of the portion of the device which is devoted to interconnecting individual logic modules.
As can be seen, an improved programmable logic array integrated circuit architecture is needed, especially an architecture providing additional possibilities for interconnections between the logic modules and improved techniques for organizing and interconnecting the programmable logic elements, including LABs and LEs.
The present invention is a programmable logic device integrated circuit incorporating a memory block. The memory block may be, but not limited to, a RAM, FIFO, or other memory, and combinations of these. In an embodiment, the memory block is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. Further, the organization of memory block may have variable word size and depth size. The memory block is coupled to a programmable interconnect array. Signals from the programmable interconnect array may be programmably coupled to the data, address, control inputs, and other inputs of the memory block. Data output and status flag signals from the memory block may be programmably coupled to the programmable interconnect array. Signals between the various PLD components and the memory block may be interconnected via the programmable interconnect array.
In particular, the present invention is a programmable logic array integrated circuit including a first plurality of conductors, extending along a first dimension of a two-dimensional array; a second plurality of conductors, extending along a second dimension of the two-dimensional array, where the second plurality of conductors is programmably coupled to the first plurality of conductors; a plurality of logic array blocks, programmably coupled to the first plurality of conductors and second plurality of conductors; and a memory block, programmably coupled to the first plurality of conductors and the second plurality of conductors. Furthermore, the memory block is programmably configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode. In a further embodiment, a word size and a depth size for the memory block are programmably selectable.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.